1. Field of the Invention
The invention relates to a semiconductor wafer having a front side, a rear side and an edge which runs along the circumference of the semiconductor wafer and which connects the front side and the rear side and which has a defined edge profile, the edge profile being substantially constant over the entire circumference of the semiconductor wafer. It also relates to a multiplicity of semiconductor wafers, the edge profile being substantially constant from semiconductor wafer to semiconductor wafer. Moreover, the invention relates to a method for producing semiconductor wafers of this type.
2. Background Art
Semiconductor wafers, in particular silicon wafers, used for the production of microelectronic components, are produced by means of a multiplicity of machining steps. The first step involves producing a polycrystalline or monocrystalline ingot made from the semiconductor material. The ingot is separated into wafers, by means of which the crystal lattice damage caused by the separation is eliminated in a plurality of machining steps and the wafers are brought to a highly precise geometrical form.
The required flatness and plane-parallelism are imparted to the surfaces of the semiconductor wafers by suitable combinations of different treatments, for example single- or double-side lapping, etching and single- or double-side polishing. In addition, a defined edge profile is produced by edge rounding and edge polishing.
It became apparent, however, that the precision and accuracy of the edge profile achieved in accordance with the prior art no longer sufficed for semiconductor wafers used for producing the latest generations of microelectronic components. Relationships have recently been ascertained to an increased extent, between the edge profile and its precision and accuracy, and the yield in the production lines for components.
In accordance with the prior art, the edge profile of semiconductor wafers could only be measured with limited precision and accuracy. Moreover, owing to the type of measuring method, it was not possible to effect measurement over the entire circumference of the semiconductor wafers. The measurement has hitherto generally been effected by profile projection. In this case, the edge profile is projected by means of a light source parallel to the planar surfaces of the semiconductor wafer, the shadow casting by the edge profile parallel to the wafer circumferences recorded by means of a camera and then evaluated by suitable image processing methods and mathematical algorithms. No measurement was thereby possible in the region of the orientation features that are generally provided on the semiconductor wafers. A notch or a flattened region (“flat”) on the circumference of the semiconductor wafer generally serve as an orientation feature. Although profile projection also functions, in principle, with non-polished edges, it does so with limited accuracy. The latter is dependent on the roughness of the surface in the region of the edge since a rougher edge leads to more scattered light and the profile is therefore no longer defined as well in the shadow casting. Moreover, profile projection does not enable measurement of the edge profile in the region of the notch or flat. Since the edge profile could be precisely determined only in the case of a polished edge, the state of the wafer edge before and after different process steps could only be compared with limited accuracy by means of profile projection. Therefore, process control of all the machining steps which alter the edge profile, in particular the edge machining steps, was also possible only to a very limited extent. Accordingly, the edge profiles of semiconductor wafers varied considerably both along the wafer circumference and in the region of the notch or flat even in the case of nominally identical specifications.
In order to solve this problem, JP 2003-017444 proposed determining the material removal during edge rounding, edge grinding and edge polishing by measurement of small depressions introduced into the semiconductor wafer for this purpose. As an alternative, U.S. Pat. No. 6,722,954 B2 describes measurement of material removal at a layer made of polycrystalline silicon specifically applied to a test wafer for this purpose. This method is complicated and is therefore not suitable for continuous process control. Moreover, the measurement is not possible on the semiconductor wafers themselves, but rather on only specially prepared test wafers.
It was furthermore attempted, by means of suitable process implementation during grinding of the front and rear sides of the semiconductor wafers, to alter the length of the facets provided on the two sides of the semiconductor wafers in a controlled manner, as disclosed in EP 0971398 A1 or U.S. Pat. No. 6,465,328 B1. Thus, EP 0971398 A1 describes a process flow in which the edge rounding is not effected directly after the separation of the semiconductor ingot into wafers, but rather only after a grinding step, which has the effect that all the wafers have an identical thickness. This is intended to ensure an identical length and height of the facets (“chamfer”) for all the wafers. It has been found, however, that this measure does not suffice to ensure a defined and uniform edge profile in the finished machined semiconductor wafers as well.
To summarize, the form of the edge profile has hitherto been determined only by measuring methods of limited accuracy. The material removal in the region of the wafer edge is additionally controlled, if appropriate, by means of auxiliary constructions such as polycrystalline silicon layers or small holes produced intentionally. Accurate tracking of the profile form of the wafer edge over all the process steps is therefore not possible, in particular not in the region of the notch or flat. The edge profile of correspondingly fabricated semiconductor wafers is therefore subject to fluctuation over a wide range.